The differential transistor pair circuit is a widely-used building block in integrated circuits. An example of a class A differential input circuit, comprised of NPN bipolar junction transistors, is shown in FIG. 1. The small-signal input is usually applied differentially to the bases of transistors Q1 and Q2, and the output is obtained at the collectors. The DC current (hence the class A designation) in the differential pair is set by a constant current source I.sub.ee connected to the emitters. The output characteristic is defined by the well-known equation: ##EQU1##
where .DELTA.v is the differential input voltage (vi+-vi-), .DELTA.i is the differential output current (io+-io-), I.sub.ee is the DC bias current of the differential pair, and V.sub.T is the thermal voltage kT/q.
Advantages of the differential pair may be summarized as:
1) Even-order distortion is suppressed due to the balanced nature of the circuit. PA0 2) Rejection of common-mode signals is high. PA0 3) Rejection of power supply noise and spurious signals is high. PA0 4) The circuit topology is compatible with low cost integrated circuit process technologies.
A disadvantage of the differential input pair is that it has limited input dynamic range in linear applications (i.e. differential inputs larger than a few V.sub.T result in highly nonlinear performance).
Some previous attempts to improve the dynamic range of the basic differential pair have been made. For example, in a well-known technique, emitter degeneration resistors are employed at the emitters of the transistors to linearize the input. The scheme, unfortunately, has the added costs of higher noise due to the resistors, and lower transconductance gain: ##EQU2##
where g.sub.m is the transconductance of the individual transistors and R.sub.e is the resistive emitter degeneration. For a given R.sub.e, it is also common to increase linearity through use of higher static bias (which increases transistor g.sub.m), but this approach increases static power consumption and circuit noise.
A circuit implemented in MOS which attempts to deal with the non-linearity problem of the differential pair is disclosed in Zhenhua Wang, "A Linearized Source-coupled Pair with a Dynamic Bias Current," Microelectronics Journal, 23 (1992) 301-304. This is achieved by adding a dynamic current to the constant bias current. More particularly, the differential pair is implemented in MOS as a pair of source-coupled N-type transistors to which is connected an additional pair of source-coupled N-type transistors. This additional pair has its gates connected to the gates of the first pair and a common drain. With the use of current mirrors the sum of the drain currents obtained in the second pair is transferred to the sources of the first pair. The effect is that a dynamic bias current proportional to the square of the input signal voltage is added to a constant bias current.
One drawback of this approach is that it requires two current mirrors each of which introduces delay causing the dynamic bias to lag the input signal thereby limiting the upper bandwidth of the circuit. As well, one of the current mirrors (the one connected to the drains of the second differential pair) has to be formed of P-type transistors and this again limits the high frequency response because the gain of P-type devices at high frequencies is low. Additionally, the dynamic portion of the bias is based on a square law function but this specific type of dynamic bias may not always be what is desired or necessary to improve the circuit performance.
Therefore, there is a need for an improved dynamic biasing technique which overcomes or lessens one or more of these problems.